1. Field of the Invention
The present invention relates to a semiconductor memory device such as ROM (read only memory) and RAM (random access memory). In particular, the present invention relates to techniques for a miniaturized semiconductor memory device to redress faults in word lines caused by leaks, broken connections and the like.
2. Description of the Related Art
It is well know that, in order to redress faults present within a memory cell array forming a semiconductor memory device and increase the yield, it is effective to form the memory cell array as a redundant structure.
An example of a redundant structure is one in which, in RAM and the like, lines (row lines and column lines) of spare memory cells are provided in advance inside the semiconductor memory device during the manufacturing process and, if it is discovered during the testing process that there are faults in the memory cell array, the faults are redressed by replacing the line containing the faults with the spare row line or column line.
However, it is not possible to employ a redundant structure such as that described above in mask ROM and the like. In mask ROM, because the memory cell data is programmed in the manufacturing process, as the locations where faults are generated are not discovered in advance during the manufacturing process, it is not possible to program spare lines in the manufacturing process. Namely, even if it is discovered afterwards in the testing process that there are faults in the memory cell array, it is not possible to replace the faulty portion with a spare line as it is with RAM.
Therefore, in mask ROM and the like, instead of providing spare lines, faults are redressed by error correction using ECC (error checking and correcting code). By performing this type of error correction, if the faults are of several bits size, error redress is possible without overly increasing the ECC bit number. Moreover, the more the ECC bit number is increased, the more bit number errors it is possible to correct. However, as increasing the ECC bit number is directly related to increased chip size, this is not preferable. Furthermore, naturally, because there is not an unlimited number of areas where ECC allocation is possible, when there is a large number of faulty memory cells, it is not possible to correct all errors. In such cases, it is necessary to discard chips whose faults were the object of correction measures as faulty chips, which results in a lower yield.
However, one of the reasons why many memory cells become faulty is because of minute leaks and broken connections arising on a word line as a result of malfunctions in the manufacturing process. Firstly, a description will be given of what happens when leaks occur on a word line, with reference made to FIGS. 11A to 11C. In FIG. 11A, it will be assumed that, in the ROM, a single driver 200 simultaneously drives four word lines 2011 to 2014. In the same diagram, a leak is shown as occurring at the point X on the word line 2014.
Here, the reason why a single driver is driving a plurality of word lines is because it is becoming difficult to provide a driver for each word line due to the continuing miniaturization of semiconductor memory devices. Namely, through miniaturization, because the size of the memory cells becomes smaller compared with the size of the driver, the trend is for the size of the driver to become relatively larger. In ROM and the like, in particular, because a memory cell can be formed from a single transistor, the size of the driver becomes larger by that amount as compared with the size of the memory cell. Therefore, the problem arises that, if a driver is provided for each word line, the surface area increases. As a result, the structure in which a single driver is provided for a plurality of word lines is currently the most common one.
As is shown in FIG. 11A, when malfunctions arise due to various reasons in the manufacturing process, in some cases, it is equivalent to a high resistance resistive element being present between the ground and the word line 2014 on the substrate or the chip. In such cases, a leak occurs at the point X shown in FIG. 11A. Here, FIG. 11B shows an equivalent circuit corresponding to the structure shown in FIG. 11A, specifically, an equivalent circuit for when the driver 200 supplies a high level (hereinafter abbreviated to xe2x80x9cHxe2x80x9d) is shown only for the word line 2014.
In FIG. 11B, the symbol Vi indicates the potential of the word line 2014 in the vicinity of the output end (namely, the end near the word line) of the driver 200; the symbol Vxb indicates the potential of the word line 2014 at the point X in FIG. 11A; the symbol Vb indicates the potential at the far end of the word line 2014 as seen from the driver 200; the symbol Ra indicates a resistive element corresponding to resistance values from the near end of the word line 2014 to the X point; the symbol Rb indicates a resistive element corresponding to resistance values from the X point to the far end of the word line 2014; and the symbol Rx indicates a resistive element corresponding to resistance values from the X point to the substrate (or ground wiring).
FIG. 11C shows the relationship between the potential on the word line and the distance (horizontal axis) taking the output end of the driver 200 as a reference with attention centering on the word line 2014. Here, when memory data is read from a memory cell, the memory cell that is being read is turned on or off (referred to below as xe2x80x9con cellsxe2x80x9d and xe2x80x9coff cellsxe2x80x9d) in accordance with the memory data, and from that it is determined whether or not current is flowing through the bit line. Here, a bit line is also called a digit line or a data line. As a result, it is possible to determine the data stored in the relevant memory cell. In order to do this, it is necessary to set the word line potential supplied to the gate terminal of the cell transistor forming the memory cell to the necessary level (namely, to the threshold voltage of the cell transistor) or higher. The xe2x80x9cVt of On cellxe2x80x9d shown in FIG. 11C represents this threshold voltage.
As is shown in FIG. 11C, the potential of the word line 2014 from the vicinity of the Xt point (omitted from FIG. 11B) positioned nearer the driver 200 than is the X point is less than the xe2x80x9cVt of On cellxe2x80x9d due to the effects of the leakage problems at the X point in FIG. 11A. Moreover, beyond (i.e. towards the far end side) the Xt point as well, the potential of the word line 2014 continues to fall up to the X point. At the X point in FIG. 11A, the potential of the word line 2014 changes to the potential Vxb, and at the far end of the word line 2014, the potential of the word line 2014 changes to the potential Vb which is substantially equivalent to the potential Vxb.
In this way, the gate potentials of the cell transistors forming each memory cell connected to the word line 2014 do not reach the threshold value on the far end side of the Xt point. Therefore, these memory cells end up being always off which results in it being impossible to read of all of these memory cells. As described above, even if only a very minute leak occurs in a word line, reading of all of the memory cells towards the far end side of the location where the leak occurs becomes impossible. Accordingly, if the leak occurs at the near end of the word line, then all of the memory cells connected to that word line end up becoming unreadable.
Next, a description will be given of what happens when a broken connection occurs on a word line with reference made to FIGS. 12A to 12C. In these figures, the same elements as shown in FIGS. 11A to 11C are shown when a broken connection has occurred. Accordingly, in FIGS. 12A to 12C, the same structural elements and signal names as were shown in FIGS. 11A to 11C have the same descriptive symbols allocated thereto.
In FIG. 12A, it will be assumed that a broken connection has occurred at the point X on the word line 2014. As a result, the potential on the word line is sufficiently high compared to the xe2x80x9cVt of On cellxe2x80x9d as far as the Xu point which is slightly closer to the near end side than the X point, moreover, the potential on the word line is substantially fixed. However, no potential is able to be supplied on the far end side of the X point which is where the broken connection has occurred. Therefore, the far end side of the Xu point shown in FIG. 12C becomes completely independent and floating, as is shown in FIG. 12B and the potential of the word line cannot be set. Therefore, the Xu point becomes a boundary with the potential of the word line dropping abruptly on the far end side thereof and falling far short of the xe2x80x9cVt of On cellxe2x80x9d. Accordingly, in the same way as when a leak occurs on the word line, if a broken connection occurs on a word line, reading of all of the memory cells connected to the word line on the far end side of the location of the broken connection becomes impossible.
As described above, if malfunctions such as leaks and broken connections occur, even if the actual memory cell itself is not faulty, reading of the memory cell on the far end side from the location of the malfunction is not possible.
It should be noted that the bit width of one byte of data output from the semiconductor memory device is normally one of 8, 16, 32, or 64 bits and this data is read from a plurality of memory cells connected to the same word line. Therefore, if malfunctions such as those described above occur, the number of bits that cannot be read contained in one byte increases and, even if error correction using ECC is performed, the possibility that the faults will not be able to be redressed increases. In cases such as this, the chip itself becomes unusable.
Here, an EEPROM (electrically erasable and programmable ROM) disclosed in Japanese Unexamined Patent Application, First Publication No. Hei 1-205794 may be given as an example of a semiconductor memory device for dealing with word line faults using ECC. This publication describes how, in order to make correction even of word line faults possible using ECC, the word line is divided and a high voltage switch (a type of buffer) is provided for raising the word line potential in each of the divided lines. By using this type of structure, even if there are several leaks in a word line, it is possible to limit the faulty memory cell to one bit and to perform correction using ECC. However, as described above, the miniaturization of semiconductor memory devices has progressed in recent times and the spaces required for providing a buffer no longer exists. Consequently, the providing of a plurality of buffers, as described in the above publication, can no longer be said to be a viable practical solution.
Note that, problems with conventional semiconductor memory devices related to ROM have been pointed out, however, the same type of problems occur in semiconductor memory devices other than ROM. Namely, if malfunctions caused by leaks and broken connections occur in a word line in RAM or the like, then the exact same problem occurs of it not being possible to read memory cells connected to the word line on the far end side of the location of the malfunction. To be sure, in the case of RAM and the like, it is possible to deal with faults in the word line by providing lines of spare memory cells, however, if it were possible to redress faults without having to use such spare lines, the size of the chip could then be reduced by the corresponding spare line amount.
Accordingly, the aim of the present invention is to provide a semiconductor memory device capable of redressing faults, when faults such as leaks and broken connections occur in a word line, substantially without increasing the chip size and without generating layout problems such as the placement of a driver being made more difficult due to increasing miniaturization.
Therefore, in the present invention, the drive section folds back a drive signal supplied to a particular word line to at least one other word line at the far end side of the particular word line as seen from the drive section. As a result, even if faults such as leaks or broken connections occur on a particular word line caused by malfunctions during manufacturing, a drive signal is supplied from the output end of the drive section to the location of the fault by a particular word line and a drive signal is supplied from the far end of a particular word line to the location of the fault via another word line and a folding section. In semiconductor memory devices in the related art, the potential from the location of the fault to the far end of a particular word line falls due to the fault in the word line, however, because it is possible to compensate for this fall in voltage according to the present invention, it is possible to guarantee that the voltage supplied to all of the memory cells connected to a particular word line will be above a threshold voltage. Therefore, the above fault in the word line can be redressed and an increase in the yield achieved.
Moreover, in the present invention, it is possible to connect by folding using wires any one word line and other word line and to form these wires and both these word lines in the same wire layer. As a result, because it is possible to redress faults in the word line without providing extra contact, it is possible to reduce the surface area required for the wires compared with when contact or the like is provided. Moreover, other than the folding section, because originally existing word lines are diverted, basically, it amounts to no more than adding a short length of wiring in order to make a connection between word lines. Accordingly, it is possible to keep the increase in the surface area that is needed to redress the faults in the word line as small as possible.
Further, in the present invention, it is also possible to arrange a plurality of word lines that are connected in a loop configuration in a concentric pattern. If this is done, it is possible to arrange the wiring such that this plurality of word line loops do not intersect each other. If the plurality of word line loops are made to temporarily intersect each other, another wiring layer needs to be provided, however, if this is done, then contact becomes necessary. In contrast to this, by forming a concentric pattern, contact and the like is not required thereby allowing the surface area to be correspondingly reduced.
Moreover, in the present invention, when there is an error in the original data, it is possible to correct this error using error correction codes and output error free data to the outside. Even if an error correction function is provided in a semiconductor memory device which is incapable of forming memory cells in redundant structures, when a plurality of memory cells have been rendered faulty due to a fault in a word line, it is not possible to perform a full correction using error correction codes. Therefore, the end result is that the chip has to be discarded. In contrast to this, according to the present invention, even in a semiconductor memory device that is incapable of forming memory cells in redundant structures, it is possible to redress faults in a number of memory cells that are caused by faults in a word line and to thereby achieve an improvement in the yield.
Furthermore, in the present invention, when a plurality of memory cells are driven simultaneously by the same drive signal, it is also possible to fold the drive signals so that they do not intersect selection signals for selecting a particular memory cell. As a result, because it is possible to place the wiring for the selection signal and the drive signal on the same wiring layer, contact and the like is not required as compared with when the selection signals and drive signals are intersected, thereby allowing the surface area to be correspondingly reduced.
Moreover, in the present invention, it is also possible to provide drive signals that are inverted relative to each other for a particular word line and for other word line, and also to invert the drive signal when a drive signal is folded from the particular word line to another word line. As a result of this, it is possible to redress faults in the word line and achieve an improvement in the yield even for DRAM and the like which are not allowed to simultaneously activate a plurality of word lines.